Semiconductor Device With Self-Aligned Back Side Features

ABSTRACT

Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

BACKGROUND OF THE INVENTION

The production of semiconductor devices at decreasing geometries and atlower costs has long been recognized as one of the key contributingfactors to the widespread benefits of the digital age. The cost of asemiconductor device is set largely by the size of the substrate, thecost of materials that are consumed as the substrate is processed, andby the amount of capital overhead that is assignable to each part. Thefirst two contributors to cost can be reduced by decreasing the size ofthe device, and by utilizing readily available materials. Capitaloverhead costs can be decreased by using readily available manufacturingequipment, and through the development of processing techniques thateliminate the need for more exotic equipment and reduce the time ittakes to build each device. These processing techniques are sometimesassociated with distinctive manufacturing features that provide evidenceof how the device was made.

A self-aligned gate is a manufacturing feature that is indicative of aparticular processing technique that can be described with reference toFIG. 1. Semiconductor wafer 100 comprises a substrate 101 covered bygate 102. As illustrated, gate 102 includes a photomask 103, a gateelectrode 104, and a gate insulator 105. At this point in the process,photomask 103 has been used to create the gate stack. In other words,gate electrode 104 and gate insulator 105 previously had additionalportions such that they extended lateral across the surface of substrate101. Photomask 103 was then used to shield the gate stack while thoseadditional portions were removed. Once gate 102 has been formed,photomask 103 can be put to use in another processing step. Asillustrated in FIG. 1, gate 102 can serve as a mask to shield channel107 while wafer 100 is exposed to a diffusion of dopants 108. As aresult, photomask 103 can be used to not only form the gate stack, butalso to create the source and drain regions of the transistor 109.Therefore, a different mask is not required for the creation of gatestack 102 and source and drain regions 109.

In addition to reducing the number of processing steps required, aself-aligned gate process produces an additional benefit in that theresulting device has superior characteristics when compared to devicesformed according to certain alternative processing methodologies. Theperformance of a transistor is directly impacted by the interdependenceof the gate, channel, source, and drain regions of the transistor. Inparticular, it is important to tightly control the location of thesource-channel and drain-channel junctions relative to the gate of thetransistor. As the same mask is used to form both the gate stack and thesource and drain regions in a self-aligned gate process, errorsresulting from the misalignment of two different masks are eliminated.The self-aligned gate process therefore provides for both a more costeffective and functionally superior device.

SUMMARY OF INVENTION

In one embodiment, a method comprises forming a gate on a semiconductoron insulator wafer. The semiconductor on insulator wafer comprises adevice region, a buried insulator, and a substrate. The method alsocomprises applying a treatment to the semiconductor on insulator waferusing the gate as a mask. The treatment creates a treated insulatorregion in the buried insulator. The method also comprises removing atleast a portion of the substrate. The method also comprises selectivelyremoving the treated insulator region from the buried insulator to forma remaining insulator region after removing the portion of thesubstrate.

In another embodiment, a method comprises forming a gate on asemiconductor on insulator wafer. The semiconductor on insulator wafercomprises a device region, a buried insulator, and a substrate. Theexemplary method further comprises applying a treatment to thesemiconductor on insulator wafer using the gate as a mask. The treatmentcreates a treated insulator region in the buried insulator. Theexemplary method also comprises removing at least a portion of thesubstrate. The exemplary method also comprises, selectively removing thetreated insulator region from the buried insulator to form a remaininginsulator region after removing that portion of the substrate.

In another embodiment, a semiconductor device comprises a gate formed ona semiconductor on insulator wafer. The semiconductor on insulator wafercomprises a device region and a buried insulator. The gate is formed ona top side of the device region. The device region is less than 100nanometers thick. The semiconductor device also comprises a depositedlayer located: (i) in an excavated region of the buried insulator; (ii)on a back side of the device region; and (iii) along a vertical edge ofa remaining region of the buried insulator. A vertical edge of the gateis aligned to the vertical edge of the remaining region of the buriedinsulator within a margin of error. The margin of error is less than 80nanometers.

FIG. 2 illustrates a semiconductor on insulator (SOI) structure 200 thatincludes semiconductor on insulator wafer 201, contact layer 202, andmetallization layers 203. The SOI wafer 201 in turn comprises substrate204, insulator layer 205, and active device layer 206. Substrate 204 canbe a semiconductor material such as silicon. Insulator layer 205 can bea dielectric such as silicon dioxide formed through the oxidation ofsubstrate 204. Active device layer 206 can include transistors thatconduct the signal processing or power operations of device 200. Asdrawn, gate 207 serves as the gate for a transistor having a channel inactive device layer 206 immediately below gate 207. Active device layer206 is coupled to metallization layers 203 via contact layer 202. Theselayers can include a combination of dopants, dielectrics, polysilicon,metal wiring, passivation, and other layers, materials or componentsthat are present after circuitry has been formed therein. The circuitrymay include metal wiring, passive devices such as resistors, capacitors,and inductors; and active devices such as transistors and diodes.

As used herein and in the appended claims, the “top” of SOI structure200 references a top surface 208 while the “bottom” of SOI structure 200references a bottom surface 209. This orientation scheme persistsregardless of the relative orientation of the SOI structure 200 to otherframes of reference, and the removal of layers from, or the addition oflayers to the SOI structure 200. Therefore, the active layer 206 isalways “above” the insulator layer 205. In addition, a vectororiginating in the center of active layer 206 and extending towards thebottom surface 209 will always point in the direction of the “back side”of the SOI structure 200 regardless of the relative orientation of theSOI structure 200 to other frames of references, and the removal oflayers from, or the addition of layers to the 501 structure 200.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a self-aligned implant for forming the source anddrain of a transistor.

FIG. 2 illustrates a semiconductor on insulator structure.

FIG. 3 illustrates a flow chart of a process for producing asemiconductor device with self-aligned back side features.

FIG. 4a-e illustrate a semiconductor structure at various stages of theprocess described with reference to FIG. 3.

FIG. 5 illustrates the effect of a self-aligned back side strain layeron the channel of a transistor.

FIG. 6 illustrates a flow chart of a process for producing asemiconductor device with a dual gate transistor and self-aligned backside features.

FIG. 7a-e illustrate a semiconductor structure at various stages of theprocess described with reference to FIG. 6.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference now will be made in detail to embodiments of the disclosedinvention, one or more examples of which are illustrated in theaccompanying drawings. Each example is provided by way of explanation ofthe present technology, not as a limitation of the present technology.In fact, it will be apparent to those skilled in the art thatmodifications and variations can be made in the present technologywithout departing from the spirit and scope thereof. For instance,features illustrated or described as part of one embodiment may be usedwith another embodiment to yield a still further embodiment. Thus, it isintended that the present subject matter covers all such modificationsand variations within the scope of the appended claims and theirequivalents.

Active device layer 206 of semiconductor on insulator (SOI) structure200 is a critical region in terms of the performance of thesemiconductor device of which structure 200 is a part. In order tocreate active devices with a desired characteristic, efforts need to betaken to protect the device layer from processing steps that introduceexcessive variation into the active layer. For example, it is generallybeneficial to not disrupt the interface between active device layer 206and insulator layer 205. In particular, in the region of active devicelayer 206 in which a channel is to be formed, the interruption of thisinterface may create dangling bonds that will alter the relationship ofthe voltage in the gate electrode of gate 207 to the current in thechannel region, and may deleteriously degrade the mobility of carries inthe channel resulting in a device that cannot operate at high frequency.However, benefits can arise from patterning the insulator layer 205 fromthe back side such that different materials can be placed in closeproximity to the channel of an active device without overly disruptingthe active layer. For example, thermal dissipation layers can be placedin close proximity to the channel regions of active devices in activedevice layer 206 to channel heat away from the active devices. Asanother example, strain layers can be deposited in close proximity tothe channel regions of the active devices to enhance the mobility ofcarriers in the channel. As a further example, electrical contacts canbe formed through a patterned insulator that need to be aligned withcontact regions that lie in or above active device layer 206.

A method for producing a semiconductor structure with self-aligned backside features can be described with reference to the flow chart in FIG.3 and the structure cross sections in FIGS. 4a-e . The process of FIG. 3begins with step 301 in which a gate is formed on an SOI wafer. The gatecan be the gate of a field effect transistor (FET) which can be ametal-oxide-semiconductor (MOS) FET or an insulated gate bipolarjunction transistor (IGBT). The gate could also be the gate of any kindof FET including a FinFET, lateral diffusion MOS (LDMOS), or a verticaldevice. The active layer may provide a channel for fully depleted (FD)FETand may serve as an ultrathin body region for such a device. The gatewill generally include an insulator and a gate electrode. For example,the gate insulator could be silicon dioxide and the gate electrode couldbe a layer of polysilicon formed on the gate insulator. The gateelectrode could also comprise a metal, such as copper, tungsten, ormolybdenum, or a metal silicide. The gate could also include additionalinsulators or layers of passivation to isolate the gate. For example,the gate could include sidewall spacers covering the gate stack in avertical direction, and could include a gate cap covering the gate stackin a lateral direction opposite the gate insulator. Finally, the gatecould also include a layer of photoresist or some other form of hardmask used to form the gate stack from layers of material with greaterlateral extents than the final gate stack. These layers could bepermanent features of the gate or they could be temporary layers thatare removed before the device is finalized.

SOI structure 400 in FIG. 4a includes SOI wafer 401 having substrate405, buried insulator layer 406, and active device layer 407. Asmentioned previously, substrate 405 can comprise a semiconductor such assilicon or an insulator such as sapphire. In situations where substrate405 is an insulator, there may not be a distinction between buriedinsulator layer 406 and substrate 405. Buried insulator layer 406 couldalso be formed through the implantation of ions into a donor wafer, andsubstrate 405 could also be a handle wafer used to steady active devicelayer 407 as it is separated from that donor wafer. In situations wheresubstrate 405 is silicon, buried insulator layer 405 could comprisesilicon dioxide formed through the oxidation of substrate 405. In thesesituations, active device layer 407 can be formed through epitaxy.Alternatively, buried insulator layer 406 can be formed in a uniformsubstrate through the application of a SIMOX process. Regardless of theparticular process used to prepare SOI wafer 401, buried insulator layer406 can be referred to as a buried insulator because it is covered on atop side by active device layer 407 and covered on its back side bysubstrate 405. The term buried insulator can be used to describe thislayer even if the substrate or active layers are removed to expose theinsulator (i.e., the term “buried” refers to the physical regionregardless of whether or not it remains buried in a finished device).

SOI structure 400 in FIG. 4a further illustrates gate 408 formed on thetop side of the device region. As illustrate, gate 408 comprises threelayers of material. Gate insulator 409 covers a portion of active deviceregion 407 that will serve as the channel of a device formed in theactive device region 407. Gate insulator 409 is covered by gateelectrode 410. In this particular example, gate 408 also includes alayer of photoresist 411 that covers gate electrode 410. However, asmentioned previously, gate 408 might not include this additional layer,and the layer may or may not be a permanent feature of gate 408. In theillustrated example, photoresist 411 is removed from gate stack 408before the device is finalized. However, photoresist 411 could also bereplaced in the figure with a dielectric that will serve as a mask andas a permanent portion of the gate.

Process 300 continues with step 302 in which a treatment is applied tothe SOI wafer using the gate as a mask. The treatment forms a treatedinsulator region in the buried insulator layer. In specific approaches,the treatment is applied to the top side of the SOI wafer. For example,the treatment could comprise the diffusion of dopant ions into theactive layer and buried insulator. As another example, the treatmentcould comprise an ion implant to dope the buried insulator layer. Thetreatment uses the gate as a mask such that the treatment is effectivelyself-aligned. However, the gate could be used as either a negative orpositive mask such that the treated insulator region could be formed inthe buried insulator layer below the gate, or outside the lateral scopeof the gate. The treatment could be applied in a wafer level processsuch that multiple gates on multiple devices would provide the patternfor the treated insulator layer. In situations in which the gate actedas a negative mask, the first exposure would prime the insulator layerthat was outside the lateral scope of the gate to withstand a secondprocessing step meant to ultimately form the treated insulator regionwithin the lateral scope of the gate. In a particular example, thetreatment will be a self-aligned ion implant into a buried oxide layerof a silicon on oxide wafer to form a doped region of the buried oxidethat is aligned with, but outside the lateral scope of, the channels ofthe wafer.

SOI structure 400 in FIG. 4a further illustrates ion bombardment 412which is directed to the top side of SOI wafer 401 using gate 408 as amask. The ion bombardment could involve the implantation of dopant ionsinto buried insulator layer 406. The energy of the ion bombardment couldbe tuned to focus its effect on the insulator layer 406 while minimizingdamage to active device layer 407. The ion bombardment could also betuned to only affect a portion of buried insulator layer 406 such thatthe treated insulator region would be distinguishable from the untreatedinsulator region in both a lateral and vertical dimension. Inparticular, the treated insulator region could be positioned towards theback side of buried insulator layer 406 such that the treated insulatorregion was below portions of untreated insulator as well as to the leftand right of untreated insulator.

Ion bombardment 412 could comprise various ion implant species. Forexample, the bombardment could comprise boron, phosphorous, or arsenic.In particular, the ion bombardment 412 could comprise dopant ions havinga lower atomic weight than carbon and greater than lithium. In specificapproaches, ion bombardment 412 will be conducted through regions of asilicon active device layer that may ultimately form the source anddrain regions of a FET or the emitter of an IGBT. As such, the dopantions can be chosen to minimize damage to these regions. While dopantions that have low atomic weights are less likely to damage the activelayer as they pass through, they are also less likely to be effective intreating the buried insulator to the extent that it can be selectivelyprocessed. Dopant ions with atomic weights that are less than carbon,but greater than lithium, are less likely to damage the active region asthey pass through, while at the same time retaining their efficacy asthe creators of a treated insulator region.

Process 300 continues with step 303 in which a portion of the substrateis removed. In specific approaches, the substrate is removed from theback side of the SOI wafer to expose the buried insulator layer. Thesubstrate can be removed by a grinding process and may involve theapplication of a chemical-mechanical polish (CMP) processing step. Thesubstrate could be removed in a single step or a multiple step process.In particular, a rapid grind could be applied to remove a majority ofthe substrate, while a slower process with higher selectivity to theburied insulator, such as a wet etch, could be applied as a second step.During step 303, the wafer may be held in place by a vacuum chuck or analternative handler such that the back side of the SOI wafer could bereadily accessed. Alternatively, the SOI wafer could be held in place bya handle wafer attached to the top side of the SOI wafer.

Process 300 can include an addition step 304 in which a handle wafer isbonded to the 501 wafer after the treatment is applied to the 501 waferin step 302. The handle wafer can be bonded to the top side of the SOIwafer. The bond can be a permanent bond or a temporary bond. Insituations where the bond is temporary, the SOI wafer may be transferredto another permanent handle wafer at a later time. The handle wafer canprovide a stabilizing force to the active device layer of the SOI waferwhile the substrate is removed in step 303. In addition, the handlewafer can serve as a permanent feature of the overall SOI structure suchthat the handle wafer continues to provide a stabilizing force to theactive device layer after the substrate is removed. The handle wafer cancomprise a trap rich layer as described in commonly assigned U.S. Pat.No. 8,466,036 and its related patents. The handle wafer can alsocomprise additional active or passive devices that can be electricallycoupled to the active device layer of the SOI wafer.

SOI structure 420 in FIG. 4b illustrates SOI wafer 401 after treatedinsulator region 421 has been formed in buried insulator layer 406. SOIstructure 420 further illustrates how SOI wafer 401 has been bonded tohandle wafer 422 and subsequently inverted for back side processing.Handle wafer 422 can be bonded to SOI wafer 401 using a permanent ortemporary bond. Handle wafer 422 can comprise a trap rich layer and canadditionally be comprised entirely of a trap rich material. Asillustrated, mask 411 has been removed from the gate 408 at this pointin the process. However, as stated previously, mask 411 may comprise apermanent portion of the device. Active device layer 407 is illustratedwith contacts 423 connecting it to the handle wafer 422. However,contacts 423 are merely representative of the additional processing thatSOI wafer 401 will undergo prior to the bonding of handle wafer 422.Although active device layer 407 can be connected to circuitry in handlewafer 422, the contacts may also connect to metallization layers meantto route signals solely within SOI wafer 401.

Various additional layers can be added to 501 wafer 401 to liein-between active layer 406 and handle wafer 422. These layers caninclude metallization for routing signals between active devices inactive device layer 406. The number of steps that lie between differentapproaches that are in accordance with cross sections 400 and 420 caninclude any kind of processing associated with variant technologies suchas CMOS or BiCMOS. In specific approaches, standard CMOS fabricationwill continue after step 302 and continue up to the deposition ofinter-level dielectric, at which point step 304 can be executed. Inother approaches, any number of additional wafers may be added to thetop side of the SOI wafer before step 304 is executed. These additionalwafers can contain trap rich layers and may also include additionalpassive and active circuitry that can be coupled to the circuitry inactive device layer 407 using direct metal contacts, through siliconvias (TSVs), or similar structures.

SOI structure 440 in FIG. 4c illustrates the SOI wafer after substrate405 has been removed. As illustrated, substrate 405 has been completelyremoved from the back side of SOI wafer 401 to thereby expose treatedinsulator region 421. However, the substrate can also be removed in apatterned fashion. For example, the substrate might only be removedbelow certain regions of an overall die such as the regions in whichactive devices will ultimately be formed. As a further example, thesubstrate might only be removed below certain features such as theregions that lie directly below the gates such as gate 408. Inparticular, the substrate can be partially removed such that a remainingportion of the substrate continues to provide a stabilizing force toactive device layer 407 as the substrate is removed. The remainingportion of the substrate could also provide a stabilizing force toactive device layer 407 in a final device. In these approaches, a handlewafer might not be needed, or a handle wafer might only be requiredwhile the substrate is partially removed, but the remaining substratecould provide the required stabilizing force to the active device layerin a final device.

Process 300 continues with step 305 in which the treated insulatorregion is selectively removed from the buried insulator layer. Theremoval of the treated insulator region from the insulator layer forms aremaining insulator region. As the gate was used to pattern the treatedinsulator region, the remaining insulator region will be aligned to thegate and lie under the active region of the SOI structure underneath thegate. A benefit of this approach is that the insulator region is therebypatterned without the need for an additional mask.

The insulator can be removed in step 305 using any process that isselective to the treated insulator region. Thus the removal process islinked to the treatment applied in step 302. As a particular example,the treatment could be the implantation of boron ions into a buriedinsulator layer comprising silicon dioxide to form a doped oxide, andthe removal process could be a hydrofluoric etch delivered in vapor formthat would remove the doped oxide and leave the untreated silicondioxide in place. The selective removal process could comprise a wethydrofluoric etch or a vapor hydrofluoric etch. In The insulator couldalternatively be removed using a plasma etch.

SOI structure 460 in FIG. 4d illustrates SOI wafer 401 after treatedinsulator region 421 has been removed. The resulting structure includesa self-aligned feature of remaining insulator 461 on the back side of achannel in active region 407. The original SOI insulator layer has beenremoved from other portions of the wafer while it remains underneath thegates that were used to pattern the treatment applied in step 302. Asshown, the remaining insulator and the gate are both in contact with achannel formed in the device region. Depending on the selectivity of theremoval process applied in step 305, remaining insulator region 461 maybe thinner in both a lateral and vertical dimension than the originalinsulator region. However, an informed selection of the treatment toapply in step 302 and a removal process for step 305 that are both basedon the material that comprises the original buried insulator layer, willlead to a highly selective removal process that contributes to thereliable alignment of the remaining insulator region 461 to the channelof devices in active region 407.

In alternative approaches, the selective removal process in step 305will result in a negative pattern to that of the treatment applied instep 302. In an alternative step, just prior to step 305, the entireinsulator region could undergo a second treatment after being exposed bythe removal of the substrate, and then be acted upon by a selectiveremoval process such that only the insulator region that was treated instep 302 would remain. In these approaches, the first treatment servesto counteract the effect of the second treatment such that only thoseportions of the insulator that did not receive the first treatment wouldremain after the application of the selective removal process.

Although SOI structure 460 illustrates treated insulator region 421 ashaving been completely removed in certain places, the treated insulatorregion could instead by removed to various degrees at different pointsalong the lateral expanse of the back side of the SOI structure. Asmentioned previously, the treatment from step 302 could be targeted to aspecific depth of the buried insulator region such that treatedinsulator region 421 did not extend through the entire vertical expanseof the original buried insulator. For example, if the treatment fromstep 302 was targeted to just cover the back half of the insulatorlayer, the selective removal in step 305 could result in only half ofthe insulator region being removed at specific points in the overallpattern such that remaining insulator region 461 would be a raisedplateau surrounded by an expanse of thinned remaining insulator.

Process 300 continues with step 306 in which a layer is deposited. Thelayer can be deposited on the back side of the SOI wafer. The layer canbe formed on the remaining insulator region. The layer can be depositedvia a blanket deposition or it can be a targeted deposition. Thedeposition step can use a mask, or it can rely only on the patternformed by the remaining insulator region. The deposition can include achemical enhanced vapor deposition (CVD), plasma enhanced CVD, atomiclayer deposition (ALD), dielectric spin or sprat coating, or a highdensity plasma deposition (HDP). Alternatively, the layer could beformed by bringing the SOI wafer into contact with a conforming layer ofmaterial that would conform to the shape of the remaining insulatorregion. The conforming layer could be brought into contact using anadditional wafer.

Cross section 480 in FIG. 4e illustrates the 501 wafer after layer 481has been deposited on the back side of the wafer. Although only a singlelayer is illustrated, multiple layers can be deposited on the SOI waferto achieve various results. In the illustrated example, removal of thetreated insulator region exposed the device region 407, and theformation of layer 481 comprised a blanket deposition of material on theremaining insulator region 461 and the device region 407. In theillustrated example, the deposition was directed to the back side of theSOI wafer. Layer 481 could comprise a strain layer, a thermaldissipation layer, or any other region of material that would benefitfrom being patterned to surround the channels of active device in deviceregion 407.

In contrast to example illustrated in FIG. 4e , but in accordance withexamples mentioned previously, gate 408 could have a negative patternrelationship with the remaining insulator region such that the insulatorwas removed from beneath the channels but left in place in other regionsof the structure. In these examples, the deposited layer could be anelectrically insulating thermal dissipation layer. This approach wouldcarry the benefit of placing the heat dissipation layer as close aspossible to the heat generating channels of the active devices. However,these approaches would be accompanied by the risk of damage to thedelicate channels of active devices in layer 407 unless specifictolerances were selected for the processing steps involved with theselective removal of the insulator, and the deposition of layer 481.

FIG. 5 displays a cross section 500 of a transistor in an SOI devicethat has been processed in accordance with the procedure described withreference to FIG. 3. Cross section 500 includes gate 408 which wasformed on the SOI wafer. The gate includes gate electrode 501 and gateinsulator 502. The cross section also illustrates channel region 503that is associated with gate 408, and that is in contact with both theremaining insulator region 461 and the gate 408. As describedpreviously, the gate 408 is formed on a top side of device region 407.Since the gate was used to pattern remaining insulator region 461, layer481 is located in an excavated region of the buried insulator 504, on aback side of active device region 407, and along a vertical edge of theremaining insulator region 461.

Certain benefits accrue to approaches in which the edges of remaininginsulator region 461 can be reliably aligned to gate 408. The processesdescribed with reference to FIG. 3 provides a degree of alignment ofthese two features that is not otherwise attainable through reasonablecommercial efforts. Using process 300, the vertical edge of gate 408 canbe reliably aligned to the vertical edge of remaining insulator 461within a margin of error that is constrained by the thickness of activedevice layer 407, the species and implant energy of any ions used totreat the insulator layer, the concentration doping concentration of thetreated insulator region, and post implant thermal conditions that mayalter the extent of the treated insulator region. As active device layer407 decreases in thickness, the margin of error increases. As theimplant energy and weight of any ions used to treat the insulator layerincreases, the margin of error increases. As the doping concentration ofthe treated insulator region increases, the margin of error decreases.Based on simulations, approaches described with reference to FIG. 3 canprovide reliable alignment of the gate 408 and the remaining insulator461 to within a margin of error of less than 80 nanometers for a deviceregion that is less than 100 nanometers thick. Notably, process 300 canachieve reliable alignment even when the ultimate device comprises fullydepleted SOI devices with particularly thin active layers. The channelregion 503 in these situations would comprise an ultra-thin body region.

As mentioned previously, layer 481 can be a strain inducing layer. Thestrain inducing layer can be a compressive or tensile film. The straininducing layer can also induce strain in active device layer 407 througha lattice mismatch effect. For example, the strain inducing layer 481could comprise silicon germanium while active device layer 407 comprisedsilicon in which case the mismatch of the two materials would inducestrain in active device layer 407. The strain inducing layer can enhancethe mobility of carriers in the device by inducing strain 505 in channelregion 503. Strain layer 481 enhances the mobility of carriers inchannel region 503, and thereby enhances the performance of devicesformed in device layer 407. A strain layer benefits from being moreclosely aligned with the channel region because it is thereby able tomore directly exert stain on the devices while at the same time notdirectly overlapping the channel region and deleteriously altering thebehavior of the device.

Different combinations of the type of treatment applied to the insulatorlayer, and the type of strain layer deposited create different kinds ofstrain in channel region 503. As mentioned previously, depending uponthe treatment applied to the insulator layer, the gate could be used aseither a negative or positive mask such that the treated insulatorregion could be formed in the insulator layer below the gate, or outsidethe lateral scope of the gate. The strain induced by the strain layercan also be considered to exhibit a negative or positive strain in thatthe deposited film can be compressive or tensile respectively. Notably,this characteristic of the film can be independent of the pattern onwhich the film is applied. Therefore, the combination of independentlypositive or negative straining films with positive or negative patternscreates the potential for four different configurations that produce twodifferent strain profiles (i.e., a negative film with a negative patterncreates a positive strain, both negative and positive combinationscreate a negative strain, and a positive film with a negative patterncreates a positive strain). This ability to achieve a given strainprofile using different combinations provides a degree of freedom to thedesigner in that certain kinds of insulator treatment or strain layermaterials can be avoided for cost or concerns regarding technicalfeasibility.

Additional variants of layer 481 also benefit from being tightly alignedto gate 408. For example, since channels are one of the largest sourcesof heat in a semiconductor device, thermal dissipation layers benefitfrom being closely aligned to the channel region in order to minimizethe distance through which the heat must diffuse before beingefficiently removed from the device. At the same time, it is importantto keep the buried insulator in place below the channel as a thermaldissipative layer is generally a less effective substitute for theoriginal buried insulator.

After step 306, additional processing steps can be conducted to connectto the circuitry in active device layer 407 as well as to package thefinal device. For example, the deposited layer could be patterned andetched to form contacts to devices in active device layer 407 to allowexternal connect. In addition, back side metallization can be formed onthe back side of the SOI wafer to provide for interconnection betweendifferent circuit components in device layer 407. For example, the backside metallization may be used to connect a transistor to anothertransistor, a transistor to a diode, or a transistor to a passivecomponent.

FIG. 6 illustrates method 600 which continues method 300 at step 303. Inmethod 600, steps 301-304 can be conducted as described above. However,method 600 is intended to operate on a wafer with an alternativestructure to that which was described previously. Method 600 produces aself-aligned dual gate device. SOI structure 700 in FIG. 7a illustratesan SOI wafer 701 that can be processed in accordance with method 600.The starting wafer comprises many of the features of SOI wafer 401, anddiffers mainly in that substrate 702 is associated with not only buriedinsulator layer 406 and active device layer 407, but a second activelayer 703 and a second buried insulator layer 704. As show in FIG. 7a ,gate 408 is used as a mask for the implantation of dopant ions into SOIwafer 701. In contrast to method 300, the ion implant, or othertreatment used in method 600, must be controlled to pass through secondburied insulator layer 704 to instead treat buried insulator region 406and form treated insulator region 705. As before, the formation oftreated insulator region 705 leaves untreated insulator region 706 inits original state.

Any of the processing steps described with reference to process 300 canlikewise be applied to method 600 as these processing steps continue.FIG. 7b illustrates SOI structure 720 as processing continues in asimilar fashion to what was described with reference to FIG. 4b . TheSOI wafer has been inverted, and an optional handle wafer 422 has beenbonded to the top of the wafer. As mentioned previously, handle wafer422 may comprise a trap rich layer. FIG. 7c illustrates cross section740 after substrate 702 has been removed.

Method 600 continues with step 601 in which the treated insulator isremoved from the buried insulator layer. An example of this processingstep is illustrated by 501 structure 760 in FIG. 7d . SOI structure 760shows the SOI wafer after treated insulator region 705 has been removedsuch that only untreated insulator layer 706 remains. At this point inthe process, active device layer 407 is exposed while second activelayer 703 and second buried insulator layer 704 remain covered.

Method 600 continues with either step 602 or 603. In step 602, a portionof the exposed device region is removed. The device region can beremoved using remaining buried insulator 706 as a mask, or an additionalmask may be used instead. The etchant used to etch device region 407 canperform an isotropic etch and may also involve a specific chemicaletchant that is selective to second buried insulator 704. In step 603, alayer of material is deposited on the back side of the wafer. Step 603can be conducted in accordance with any of the variations of step 306discussed above.

FIG. 7e illustrates 501 structure 780 which shows SOI wafer 701 after aportion of device region 407 has been removed to form remaining deviceregion 781, and a layer 481 has been deposited on the back side of thewafer. In this situation, the remaining device region 781 serves as anadditional gate electrode for a channel formed in second device region703 while second buried insulator 704 serves as the gate insulator forthe additional gate. The resulting structure comprises a self-alignedDG-FET. In this structure, gate 408 contacts second device region 703and is associated with a channel formed in second device region 703. Theremaining device region 781 servers as a second gate electrode for thesame channel, and the remaining buried insulator 706 serves to isolateand shield remaining device region 781.

Insulator layer 406 in FIGS. 7a-e is thicker than second insulator layer704 to illustrate certain benefits that accrue to such a structure. Inparticular, in situations where the treatment to the buried insulatorlayer is an ion implantation step, the thickness of insulator layer 406makes it an easier target for implantation. At the same time, thethickness of a gate insulator is inversely proportional to certainfigures of merit associated with the transistor—such as itstransconductance. Since insulator layer 704 will serve as a gateinsulator for the additional gate, it is beneficial to make insulatorlayer 704 relatively thin. Therefore, when used with an ion implantationtreatment, process 600 is particularly amenable to the creation of ahigh performance DG-FET.

The dual gate structure illustrated in FIG. 7e benefits greatly from thedegree of alignment provided by process 300 and 600 in that misalignedgates in a DG-FET can result in extra capacitance and a commensurateloss of current drive. However, when the gates are reliably aligned witha high degree of accuracy, the speed and power dissipation of a DG-FETis substantially lower than that of a single gate FET. Therefore, thecreation of a dual gate structure according to a self-aligned process,such as process 600, can produce a superior transistor to approaches inwhich a separate mask is used to create additional gate electrode 781.The process of FIGS. 3 and 6 can reliably align the dual gates of theDG-FET with similar constraints to what was discussed above. However, inthis situation, the thickness of the buried insulator is also aconstraint on the reliability of the alignment because the implant isthrough both the buried insulator and the top active region. Based onsimulations, approaches described with reference to FIGS. 3 and 6 canprovide reliable alignment of the gate 408 and remaining device region781 to within a margin of error of less than 70 nanometers for a deviceregion that is less than 80 nanometers thick with a buried insulatorthickness of 10 nanometers. Notably, process 300 can achieve reliablealignment even when the ultimate device comprises fully depleted SOIdevices with particularly thin active layers. The channel region 503 inthese situations would comprise an ultra-thin body region.

Deposited layer 481 can take on any of the characteristics describedabove with reference to FIGS. 4e and 5. In particular, deposited layer481 can be a strain layer that enhances the mobility of carriers in thechannel formed in second device layer 704. As described previously, thefilm can be compressive or tensile. Layer 481 can also be a thermaldissipation layer. Also, as noted above with reference to FIG. 4e , SOIstructure 780 can undergo additional processing steps to connect tocircuitry in active layer 703. In addition, SOI structure 780 canundergo additional processing steps to connect gate electrode 781 tocircuitry in different wafers, on a package, or to circuitry in activelayer 703. In particular, gate electrode 781 could be connected to thesame circuitry as the gate electrode of gate 408.

Although some embodiments in the above disclosure were specificallyillustrated by cross sections wherein a gate structure is used as themask for an initial treatment of an SOI insulator layer, other featurescan be used to mask the initial treatment instead. Indeed, any featureto which back side alignment is desired could be used to pattern theapplied treatment. Depending upon the characteristics of the feature,the material used to define the feature could be used as a mask itself,or the actual mask used to pattern that feature can be used as the maskfor the initial treatment. As a particular example, the mask used topattern TSVs in the SOI wafer could also be used to apply a treatment tothe insulator. Such an approach would be useful in situations where theTSVs were intended to be connected through the back side insulator.

While the specification has been described in detail with respect tospecific embodiments of the invention, it will be appreciated that thoseskilled in the art, upon attaining an understanding of the foregoing,may readily conceive of alterations to, variations of, and equivalentsto these embodiments. These and other modifications and variations tothe present invention may be practiced by those skilled in the art,without departing from the spirit and scope of the present invention,which is more particularly set forth in the appended claims.

1-21. (canceled)
 22. A semiconductor device comprising: a gate formed ona semiconductor on insulator wafer, wherein the semiconductor oninsulator wafer comprises a device region and a buried insulator,wherein the gate is formed on a top side of the device region, andwherein the device region is less than 100 nanometers thick; and adeposited layer located: (i) in an excavated region of the buriedinsulator; (ii) on a back side of the device region; and (iii) along avertical edge of a remaining region of the buried insulator; wherein avertical edge of the gate is aligned to the vertical edge of theremaining region of the buried insulator within a margin of error; andwherein the margin of error is less than 80 nanometers.
 23. Thesemiconductor device of claim 22, wherein: the deposited layer comprisesa strain layer; and the gate contacts the device region.
 24. Thesemiconductor device of claim 22, wherein: the deposited layer comprisesa thermally conductive layer; and the gate is formed in the deviceregion.
 25. The semiconductor device of claim 22, wherein: thesemiconductor on insulator wafer comprises a second device region and asecond buried insulator; the deposited layer comprises a strain layer;the gate contacts the second device region and is associated with achannel; and the device region comprises a second gate associated withthe channel.
 26. The semiconductor device of claim 22, wherein: thesemiconductor device comprises an ultra-thin body region; and thesemiconductor device comprises a fully depleted silicon on insulatortransistor.
 27. A semiconductor device comprising: a gate formed on asemiconductor on insulator wafer, wherein the semiconductor on insulatorwafer comprises a first device region and a first buried insulatorlayer, wherein the gate is formed on a top side of the first deviceregion; a remaining portion of the first buried insulator layer formedon a back side of the gate and aligned with the gate; and a depositedlayer located: in an excavated region of the first buried insulatorlayer, on a back side of the first device region, and along a verticaledge of the remaining portion of the first buried insulator layer;wherein a vertical edge of the gate is aligned to the vertical edge ofthe remaining portion of the first buried insulator layer.
 28. Thesemiconductor device of claim 27, further comprising: a second buriedinsulator layer and a second device region formed under the gate. 29.The semiconductor device of claim 28, wherein the gate includes a gateelectrode for a channel formed in the second device region; and whereinthe first device region comprises an additional gate electrode for achannel formed in the second device region.
 30. The semiconductor deviceof claim 28, wherein the second buried insulator layer is thinner thanthe first buried insulator layer.
 31. The semiconductor device of claim27, wherein the deposited layer comprises a strain layer.
 32. Thesemiconductor device of claim 27, wherein the deposited layer comprisesa thermal dissipation layer.
 33. The semiconductor device of claim 27,wherein the gate is included in a transistor, the semiconductor devicefurther comprising: a conductive contact extending through a patternedportion of the deposited layer coupling with the transistor.